The present invention relates to digital data receivers, and more particularly to an improved serial-digital receiver that improves clock recovery signal to noise ratio (S/N), eliminates the need for a DC restorer and detects single-bit errors.
Current serial-digital video transmitters use a scrambled NRZI (Non Return to Zero Inverted) channel coding that is directly converted to ECL voltage levels for transmission. The logic "1" and logic "0" values of the channel code are converted to +400 mv and -400 mv voltage levels and launched into the input of a 75 ohm coaxial cable that represents the channel. The scrambling is required to pseudo-randomize or decorrelate the serialized data bits or channel signal voltages so as to make them pseudo independent of the data-byte patterns that represent the video image.
For example, a flat-field image represents a repeated byte pattern that serializes into a fixed, repetitive sequence that could contain long strings of "1"s or "0"s. The scrambler is a feedback shift register to pseudo-randomize the sequence such that, even if the input to the scrambler is a long string of "1"s or "0"s, the output is a balanced sequence mixture of both. The design of these LFSR (Linear Feedback Shift Register) scramblers is well known to those of ordinary skill in the art.
However it is important to note that the characteristics of the scrambler are such that some video patterns are not sufficiently randomized in the current serial-digital video standard. These pathogenic patterns have been identified and are used for stress-testing today's serial-digital systems. They are known as pathological or Serial Digital Interface (SDI) test signals. Other, possibly more complicated, scramblers could be designed that would be insensitive to these stressful signals, but such scramblers would not likely be back-compatible with existing equipment.
The reasons for using a scrambler to eliminate these long strings of "1"s and "0"s are at least twofold. First, the serial data is preferred to be converted directly to an ECL channel voltage in a self-clocking NRZ format. Long strings of "1"s and "0"s reduce the channel voltage transitions to very few and far between so that clock recovery becomes difficult to impossible. Second, the system is preferably AC coupled, and the long strings of "1"s and "0"s make DC restoring and equalizing of the channel signal for conversion to binary-digital very difficult or impossible.
From a frequency domain perspective, the scrambler acts to fill-in the broadband spectrum of the scrambled NRZI channel signal, making it more noise-like. However, despite the fact that the signal is referred to as digital, the channel signal actually is an analog signal with most of the traditional analog problems. This broadband signal should be presented to a receiver with nearly a flat frequency response for best reception. Therefore, since the transmission channel is coaxial cable with a frequency-dependent loss, an adaptive equalizer is used at the receiver to compensate for this loss. The equalizer restores the high-frequency components lost through the cable to prevent the less attenuated, low-frequency components from interfering with the attenuated high-frequency components. This is necessary to allow proper slicing of the signal voltage into the correct logic levels that the signal voltage represents.
In addition, since the low-frequency coupling is often not sufficient in practical systems, a DC restorer is also used. This is an important element since loss of these low-frequency components may be a cause of jitter in the received data. A diagram of a typical serial-digital transmitter, channel and receiver is shown in FIG. 1.
One final element is added to the channel coding, an NRZ to NRZI coder. This is a single-bit LSFR used to make the channel signal polarity independent. It is essentially a modulo-two accumulator where a logic "0" input causes no change in the output and a logic "1" input increments the output, causing it to change state. For example, a string of "1"s at the input causes an output of alternating "1" and "0" values. In this way the "1" and "0" data is communicated via the changes or transitions in the data or channel signal voltage as opposed to the actual values of the channel voltage. Since a change in the data from both a "0" to a "1" and a "1" to a "0" is detected as a logic "1", and the lack of a change as a logic "0", the polarity of the change is unimportant. Decoding the NRZI data back to NRZ is simply a matter of comparing the current data value with the immediately preceding value and, if they are different, output a "1" and, if they are the same, output a "0".
What is desired is an improved serial-digital receiver for extracting data from a transmitted data channel where the data is in NRZI format.